\doxysection{DMA2\+D\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_d_m_a2_d___type_def}{}\label{struct_d_m_a2_d___type_def}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}}


DMA2D Controller.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_afb0ef686f69afae3e9614a9b30558dcf}{CR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_a03ffbd962bae5def253311b5b385cd07}{ISR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_aede126199a74ea2a7477c1361537f3c4}{IFCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_a8f6597d73722df5394be67c0ac22fe66}{FGMAR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_a9a1b3799763c47fefd4772f10b7df91b}{FGOR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_a9d9d6051b0db4c369c7aa77c0c8740d0}{BGMAR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_a93ae9fddd0bab5c8938015a540e6371e}{BGOR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_ae98f793825b09b2b70300582d2f8a9fe}{FGPFCCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_a8e2ca425d2b5655573fd89bca5efb272}{FGCOLR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_a2469616cbbe6a9e9afa1b943f326add0}{BGPFCCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_a9dad401dfd995251a189d457bc6a5ebd}{BGCOLR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_afdbd6e3f06436d655b464e1ea804ea31}{FGCMAR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_a7b6a846a09e204c29664759983853ec0}{BGCMAR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_a50f9ee49cd295305a56ac58b96d11ded}{OPFCCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_a07566e4390ac1c55a3fd7f58dd6e33c6}{OCOLR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_a4ecac7187f1a8fcd108b14abdfb4934d}{OMAR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_a118208b8645815a2aa670e92d6277199}{OOR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_a96a187a30051332f029676b6ecd36167}{NLR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_aa78b34a419d5a35c5504f1818ef9f122}{LWR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_a5e5f5a73a2c943723044960897daccc3}{AMTCR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_a996362d8114c5c841da6c763b0df3df1}{RESERVED}} \mbox{[}236\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_a4f8c1dc3470960b18ec9e3c358d0b0ad}{FGCLUT}} \mbox{[}256\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a2_d___type_def_a2ee6a30b394faf8442becbfa8b737413}{BGCLUT}} \mbox{[}256\mbox{]}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
DMA2D Controller. 

\label{doc-variable-members}
\Hypertarget{struct_d_m_a2_d___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_d_m_a2_d___type_def_a5e5f5a73a2c943723044960897daccc3}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!AMTCR@{AMTCR}}
\index{AMTCR@{AMTCR}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{AMTCR}{AMTCR}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_a5e5f5a73a2c943723044960897daccc3} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+AMTCR}

DMA2D AHB Master Timer Configuration Register, Address offset\+: 0x4C \Hypertarget{struct_d_m_a2_d___type_def_a2ee6a30b394faf8442becbfa8b737413}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!BGCLUT@{BGCLUT}}
\index{BGCLUT@{BGCLUT}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BGCLUT}{BGCLUT}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_a2ee6a30b394faf8442becbfa8b737413} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+BGCLUT\mbox{[}256\mbox{]}}

DMA2D Background CLUT, Address offset\+:800-\/BFF \Hypertarget{struct_d_m_a2_d___type_def_a7b6a846a09e204c29664759983853ec0}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!BGCMAR@{BGCMAR}}
\index{BGCMAR@{BGCMAR}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BGCMAR}{BGCMAR}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_a7b6a846a09e204c29664759983853ec0} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+BGCMAR}

DMA2D Background CLUT Memory Address Register, Address offset\+: 0x30 \Hypertarget{struct_d_m_a2_d___type_def_a9dad401dfd995251a189d457bc6a5ebd}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!BGCOLR@{BGCOLR}}
\index{BGCOLR@{BGCOLR}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BGCOLR}{BGCOLR}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_a9dad401dfd995251a189d457bc6a5ebd} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+BGCOLR}

DMA2D Background Color Register, Address offset\+: 0x28 \Hypertarget{struct_d_m_a2_d___type_def_a9d9d6051b0db4c369c7aa77c0c8740d0}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!BGMAR@{BGMAR}}
\index{BGMAR@{BGMAR}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BGMAR}{BGMAR}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_a9d9d6051b0db4c369c7aa77c0c8740d0} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+BGMAR}

DMA2D Background Memory Address Register, Address offset\+: 0x14 \Hypertarget{struct_d_m_a2_d___type_def_a93ae9fddd0bab5c8938015a540e6371e}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!BGOR@{BGOR}}
\index{BGOR@{BGOR}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BGOR}{BGOR}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_a93ae9fddd0bab5c8938015a540e6371e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+BGOR}

DMA2D Background Offset Register, Address offset\+: 0x18 \Hypertarget{struct_d_m_a2_d___type_def_a2469616cbbe6a9e9afa1b943f326add0}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!BGPFCCR@{BGPFCCR}}
\index{BGPFCCR@{BGPFCCR}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BGPFCCR}{BGPFCCR}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_a2469616cbbe6a9e9afa1b943f326add0} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+BGPFCCR}

DMA2D Background PFC Control Register, Address offset\+: 0x24 \Hypertarget{struct_d_m_a2_d___type_def_afb0ef686f69afae3e9614a9b30558dcf}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!CR@{CR}}
\index{CR@{CR}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR}{CR}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_afb0ef686f69afae3e9614a9b30558dcf} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+CR}

DMA2D Control Register, Address offset\+: 0x00 \Hypertarget{struct_d_m_a2_d___type_def_a4f8c1dc3470960b18ec9e3c358d0b0ad}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!FGCLUT@{FGCLUT}}
\index{FGCLUT@{FGCLUT}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{FGCLUT}{FGCLUT}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_a4f8c1dc3470960b18ec9e3c358d0b0ad} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+FGCLUT\mbox{[}256\mbox{]}}

DMA2D Foreground CLUT, Address offset\+:400-\/7FF \Hypertarget{struct_d_m_a2_d___type_def_afdbd6e3f06436d655b464e1ea804ea31}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!FGCMAR@{FGCMAR}}
\index{FGCMAR@{FGCMAR}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{FGCMAR}{FGCMAR}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_afdbd6e3f06436d655b464e1ea804ea31} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+FGCMAR}

DMA2D Foreground CLUT Memory Address Register, Address offset\+: 0x2C \Hypertarget{struct_d_m_a2_d___type_def_a8e2ca425d2b5655573fd89bca5efb272}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!FGCOLR@{FGCOLR}}
\index{FGCOLR@{FGCOLR}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{FGCOLR}{FGCOLR}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_a8e2ca425d2b5655573fd89bca5efb272} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+FGCOLR}

DMA2D Foreground Color Register, Address offset\+: 0x20 \Hypertarget{struct_d_m_a2_d___type_def_a8f6597d73722df5394be67c0ac22fe66}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!FGMAR@{FGMAR}}
\index{FGMAR@{FGMAR}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{FGMAR}{FGMAR}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_a8f6597d73722df5394be67c0ac22fe66} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+FGMAR}

DMA2D Foreground Memory Address Register, Address offset\+: 0x0C \Hypertarget{struct_d_m_a2_d___type_def_a9a1b3799763c47fefd4772f10b7df91b}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!FGOR@{FGOR}}
\index{FGOR@{FGOR}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{FGOR}{FGOR}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_a9a1b3799763c47fefd4772f10b7df91b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+FGOR}

DMA2D Foreground Offset Register, Address offset\+: 0x10 \Hypertarget{struct_d_m_a2_d___type_def_ae98f793825b09b2b70300582d2f8a9fe}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!FGPFCCR@{FGPFCCR}}
\index{FGPFCCR@{FGPFCCR}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{FGPFCCR}{FGPFCCR}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_ae98f793825b09b2b70300582d2f8a9fe} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+FGPFCCR}

DMA2D Foreground PFC Control Register, Address offset\+: 0x1C \Hypertarget{struct_d_m_a2_d___type_def_aede126199a74ea2a7477c1361537f3c4}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!IFCR@{IFCR}}
\index{IFCR@{IFCR}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IFCR}{IFCR}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_aede126199a74ea2a7477c1361537f3c4} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+IFCR}

DMA2D Interrupt Flag Clear Register, Address offset\+: 0x08 \Hypertarget{struct_d_m_a2_d___type_def_a03ffbd962bae5def253311b5b385cd07}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!ISR@{ISR}}
\index{ISR@{ISR}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ISR}{ISR}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_a03ffbd962bae5def253311b5b385cd07} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+ISR}

DMA2D Interrupt Status Register, Address offset\+: 0x04 \Hypertarget{struct_d_m_a2_d___type_def_aa78b34a419d5a35c5504f1818ef9f122}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!LWR@{LWR}}
\index{LWR@{LWR}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{LWR}{LWR}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_aa78b34a419d5a35c5504f1818ef9f122} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+LWR}

DMA2D Line Watermark Register, Address offset\+: 0x48 \Hypertarget{struct_d_m_a2_d___type_def_a96a187a30051332f029676b6ecd36167}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!NLR@{NLR}}
\index{NLR@{NLR}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{NLR}{NLR}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_a96a187a30051332f029676b6ecd36167} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+NLR}

DMA2D Number of Line Register, Address offset\+: 0x44 \Hypertarget{struct_d_m_a2_d___type_def_a07566e4390ac1c55a3fd7f58dd6e33c6}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!OCOLR@{OCOLR}}
\index{OCOLR@{OCOLR}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OCOLR}{OCOLR}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_a07566e4390ac1c55a3fd7f58dd6e33c6} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+OCOLR}

DMA2D Output Color Register, Address offset\+: 0x38 \Hypertarget{struct_d_m_a2_d___type_def_a4ecac7187f1a8fcd108b14abdfb4934d}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!OMAR@{OMAR}}
\index{OMAR@{OMAR}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OMAR}{OMAR}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_a4ecac7187f1a8fcd108b14abdfb4934d} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+OMAR}

DMA2D Output Memory Address Register, Address offset\+: 0x3C \Hypertarget{struct_d_m_a2_d___type_def_a118208b8645815a2aa670e92d6277199}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!OOR@{OOR}}
\index{OOR@{OOR}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OOR}{OOR}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_a118208b8645815a2aa670e92d6277199} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+OOR}

DMA2D Output Offset Register, Address offset\+: 0x40 \Hypertarget{struct_d_m_a2_d___type_def_a50f9ee49cd295305a56ac58b96d11ded}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!OPFCCR@{OPFCCR}}
\index{OPFCCR@{OPFCCR}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OPFCCR}{OPFCCR}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_a50f9ee49cd295305a56ac58b96d11ded} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+OPFCCR}

DMA2D Output PFC Control Register, Address offset\+: 0x34 \Hypertarget{struct_d_m_a2_d___type_def_a996362d8114c5c841da6c763b0df3df1}\index{DMA2D\_TypeDef@{DMA2D\_TypeDef}!RESERVED@{RESERVED}}
\index{RESERVED@{RESERVED}!DMA2D\_TypeDef@{DMA2D\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED}{RESERVED}}
{\footnotesize\ttfamily \label{struct_d_m_a2_d___type_def_a996362d8114c5c841da6c763b0df3df1} 
uint32\+\_\+t DMA2\+D\+\_\+\+Type\+Def\+::\+RESERVED\mbox{[}236\mbox{]}}

Reserved, 0x50-\/0x3\+FF 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
